In a process for manufacturing a semiconductor integrated circuit device having a triple-well structure and two types of gate oxide film having different thicknesses in one chip, a manufacturing process in which ion implantation toward an embedded diffused layer for forming a triple-well and etching of oxide film to form two types of gate oxide film having different thicknesses in one chip is achieved by passing, preferably, one photo resist step has become one of great concerns.
The reason why a configuration having a triple-well structure and two types of gate oxide films having different thicknesses in one chip has been demanded will be described.
Firstly, necessity of a triple-well will be described. Semiconductor integrated circuit devices such as DRAMs (dynamic random access memories) and SRAMs (static random memories) are generally formed with peripheral circuit and input/output units comprising CMOSs. Their silicon substrates are formed with N-type and P-type wells. If the internal power source voltage is made lower than the external power source voltage for reduction in power consumption, it is necessary to insulate N-type wells from each other to which internal and external power source voltages are applied, respectively. In DRAMs and SRAMs, the P-type wells of memory cell unit should be electrically insulated from the other P-type wells for protecting the memory cells from electrical noises from the peripheral and input/output (I/O) circuit units.
In order to electrically insulate N-type wells from each other and P-type wells from each other in such a manner, it is necessary to provide a triple-well structure by forming an embedded diffused layer.
Necessity to use two types of gate oxide film having different thicknesses in one chip will now be described.
If the external and internal power source voltages are different in a semi conductor integrated circuit device such as DRAM and SRAM, a voltage which is higher than that of the peripheral circuit unit to which the internal power source voltage is applied is applied to the gates of MOS transistors of I/O circuit unit, to which external power source voltage is applied.
If the voltage for word line is stepped up in a memory cell unit of DRAMs and SRAMs, a voltage which is higher than that of the peripheral circuit is applied to the gates of MOS transistors of the memory cells.
If only one gate oxide film is used in one chip, the thickness of the gate oxide film should be set to meet the requirements of a MOS transistor to which the highest gate voltage is applied for assuring the reliability of the gate oxide film. Accordingly, if the external and internal power source voltages are different, or stepping up of word line voltage is conducted, the thickness of the gate oxide film should be set to meet the requirements made by the higher voltage of the I/O circuit units and memory cells.
As a result, the gate oxide film having a thickness which is larger than that the film needs will be provided in the peripheral circuit units. The thicker the gate oxide film becomes, the less the turn-on current (the current which flows through the transistor when it is conductive) of the MOS transistor becomes. This results in a low operation speed of the circuit.
On the other hand, if two types of gate oxide films having different thicknesses are formed in one chip, the operation speed of the circuit can be made faster by making the gate oxide film of the peripheral circuit unit thinner than that of the other units to increase the turn-on current of the transistor. In such a manner, it is necessary to use two types of gate oxide films having different thicknesses in one chip for making the operation speed faster.
As mentioned above, the configuration including a triple-well structure and two types of gate oxide films having different thickness in one chip is very useful.